In FPGA design, interfacing over AXI (ARM eXtensible Interface) is an increasingly popular choice due to its status as the most widespread AMBA interface, enabling the connection of potentially hundreds of Masters and Slaves in complex SoCs.
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However, it does add in an additional layer to managing IP. Time has to be spent supervising and generating IP outputs before they can be incorporated into the mainline project, and simulating the design can be a challenge in itself!
One option that significantly reduces the overhead is to choose BRAM, which helps interface to AXI without the need to handle the AXI bus directly and removes concerns about potential issues that are not related to the function of the IP.
However, there are of course plenty of variables to consider both for and against:
· BRAM interface supports AXI burst access which means high throughput is possible. Direct Memory Access (DMA) engines can be used with little effort, which is particularly useful for scatter-gather operations or other relatively slow I/O data transfer operations. A BRAM controller with full AXI can support the CDMA – giving fast data access between the custom peripherals and other memory mapped structures, such as DDR memory.
· The Test bench is simplified by a well-defined simple address and data bus model, and because multiple peripherals can be multiplexed together onto one BRAM interface bus. It is possible to run the BRAM interface and the core of the peripheral at different clock speeds by adding synchronisers to registers in the IP.
· IP Simulation can be performed in the mainline project using different source directories for each IP, which allows the IP source to be extracted and shared later or even packaged with an IP-XACT layer.
· Coding is considerably simplified. The choice of address registers and BRAM areas is placed into the hands of the designer and is easily defined with a case statement. It is easy to change and add more registers, making changes does not require running any other tools, and it is also easy to maintain – it’s all HDL. Just add in a register and synthesize/simulate (provided enough address and data bits already exist).
· Choosing BRAM may take up slightly more resources as the BRAM controller will have to be instantiated in the design.
· Read/write access must obey BRAM access; which can be seen as both an advantage, because it’s a simple read/write access, and a disadvantage, because there is no method to hold the bus off if data takes a long time to come back. However, it is possible to get around this by using status register bits or interrupts which can indicate when a slow read is ready.
· AXI re-ordering is not supported, which means that the current transaction must complete before a new one can occur. This can reduce flexibility.
Overall, it’s clear that while BRAM will not suit every FPGA design scenario, it provides a multitude of benefits that can assist significantly in a variety of situations, and the pros really do outweigh the cons in many applications.
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