⏩ TL;DR
On a dense board, two layout choices decide most of your EMC margin: how far apart you keep signal traces, and where the return current goes when a signal changes layer. Space traces at three times the dielectric height or more, and give every layer transition a nearby return path. Microvia aspect ratio and the cost of going HDI are covered in our PCB miniaturisation guide. You can check your own via geometry against IPC-2226 with the HDI Layout Checker.
Table of Contents
How much trace spacing does the 3H rule need?
The 3H rule of thumb says to keep traces no closer than three times the dielectric height, where H is the distance from the signal layer to its nearest reference plane. It is widely used, though not the only rule.
Freescale (now NXP) gives it in a 2006 application note, AN2536, as a crosstalk guideline. Texas Instruments’ High-Speed Layout Guidelines (revised 2017) works from trace width instead and suggests roughly 2 to 3 times the width. Both are starting points, so check them against your fabricator’s stack-up and, for fast edges, a simulation.
A worked example shows why HDI helps. With a 5 mil dielectric, the minimum spacing is 15 mils. Drop to a 3 mil HDI dielectric and the same rule gives 9 mils. The thinner stack-up lets you route closer together and keep the same crosstalk margin.
Two limits apply. The rule is a shortcut for microstrip routing on outer layers. For stripline, where a trace sits between two reference planes, work from the smaller of the two dielectric distances. And once rise times get fast enough to need simulation, treat 3H as a starting point and let the simulation decide.
What happens to the return path at a layer transition?
A signal that changes layer through a via does not take its return current with it automatically. That current has to find a path to the new reference plane, and the longer the detour, the larger the loop it forms and the more it radiates and picks up noise.
On a dense HDI board you add layer transitions quickly, because fine-pitch BGAs push you into microvias. Each one is a place to check:
- Does the signal move between layers that share the same reference plane, or between different ones?
- Where the references differ, is there a ground or stitching via close enough to give the return current a short route? How close is close enough depends on the board and the edge rates, so there is no single distance to quote.
- Has any routing channel cut into the plane directly beneath a high-speed signal?
Texas Instruments’ High-Speed Layout Guidelines says the return current should ideally flow beside the signal, and puts the fix plainly: “A good way to realize this is to add some ground vias around the signal via.”
Board-to-board connectors are transitions too. ByteSnap Design’s Cocoon smart home security project has three boards: a sensor board, a CPU board, and a camera board built by a separate camera specialist. The CPU board is a dense, high-speed digital design with DDR, eMMC, power and Wi-Fi, and camera data crosses between boards over MIPI. As the case study describes, we chose the connectors and did the high-speed calculations for those boards.
What do vendor layout notes say about return paths?
The same TI report is blunt about ground reference planes. It says the designer has to make sure the return current can flow directly underneath the signal trace, and that “the best solution is to avoid any slots in the ground reference plane”.
It also warns that “split ground planes act as slot antennas and radiate”.
Neither point is new, but both get easier to break as a board shrinks, which is why they belong in a layout review before routing starts.
Layout decisions
Spacing and return paths draw on the same EMC margin, so settle them together during layout rather than leaving a shielding can to patch a decision made weeks earlier.
No review can promise an EMC pass. You do your best with the stack-up and routing, and the board either passes in the chamber or it doesn’t. These checks put the odds on your side before you find out.
If heat is the tighter constraint on your board, thermal dissipation in sealed enclosures covers the copper and conduction side.
Ready to get your layout reviewed?
An EMC failure found in the test chamber costs far more than the same issue caught in layout review. ByteSnap Design's engineers check spacing and return paths before a board is routed, and while it's still easy to change.
Dunstan is a chartered electronics engineer who has been providing embedded systems design, production and consultancy to businesses around the world for over 30 years.
Dunstan graduated from Cambridge University with a degree in electronics engineering in 1992. After working in the industry for several years, he co-founded multi-award-winning electronics engineering consultancy ByteSnap Design in 2008. He then went on to launch international EV charging design consultancy Versinetic during the 2020 global lockdown.
An experienced conference speaker domestically and internationally, Dunstan covers several areas of electronics product development, including IoT, integrated software design and complex project management.
In his spare time, Dunstan enjoys hiking and astronomy.
